💠 Fab semiconductor Ụdị dị ndụ

Ntọala — ụdị dị n'azụ ọnụọgụ

Mmekọrịta ọ bụla simulator na-eji, na isi mmalite ya. Ihe na-agbanwe agbanwe akara dị ka echiche bụ nhazi ngosi.

Ọnọdụ ngwá ọrụ na-agbaso SEMI E10: na-emepụta, nkwadebe, injinia, nkwụsị a haziri na nke a na-ahazighị.

Availability = up tools / 8 · Utilization = productive tool-hours / total[1]

Ngwá ọrụ na-ada n'ụzọ enweghị usoro site n'oge ọdịda exponential; ndozi na-eche onye teknishien efu.

P(fail in Δt) = 1 − e^(−Δt/MTBF), MTBF = 250 h; repair ~ Exp(mean 6 h) once a technician is free[17][1]Echiche: oke (MTBF, ọnụego mmepụta, k, τ) bụ nhazi ngosi, ọ bụghị data sitere na fab n'ezie.

Iwu Little na-ejikọta ọrụ n'usoro, mmepụta na oge okirikiri.

CT = WIP / TH = T0 + queue / TH, T0 = 1 h[6][5]

N'ahịrị kwụsiri ike, mmepụta hà nhata ọnụego ntọhapụ, ya mere mmalite wafer a tọhapụghị bụ wafer na-agaghị apụta. Wafer na-eche ogologo oge n'etiti usoro na-emebi windo queue-time.

TH = release rate while u < 1 ⇒ wafers out ≈ Σ starts; queue wait = CT − T0 = queue / TH ≤ queue-time window (3.5 h CT in semi-tool-crash)[5][16]Echiche: oke oge okirikiri 3.5 h na-anọchi anya windo queue-time; process engineering na-esetịpụ windo n'ezie n'usoro n'usoro, a na-atụfukarị wafer mebiri ha.

Ịbịaru nso Kingman: oge ahịrị na-eto dị ka u/(1−u) — ọ na-agbawa ka ojiji na-eru nso 100 %.

CTq ≈ ((ca² + ce²)/2) · (u/(1−u)) · te[5]E gosiri maka nghọta: ahịrị simulator na-apụta site na ọbịbịa enweghị usoro na ikike enweghị usoro karịa site na usoro a.

Oke ọkwa ISO 14644-1 maka obere ihe nke nha D; na 0.1 µm ọkwa bụ log nke ntinye.

Cn = 10^N · (0.1/D)^2.08 ⇒ N = log10(C≥0.1µm)[2]

Ụlọ jikọtara nke ọma: ntinye = mmepụta ÷ (mgbanwe ikuku × olu × ọrụ nzacha).

C = G / (ACH · V · η)[13][11]Echiche: oke (MTBF, ọnụego mmepụta, k, τ) bụ nhazi ngosi, ọ bụghị data sitere na fab n'ezie.

Iwu ihe yiri fan: ike na-ebili na kubu nke ọsọ fan.

P_fan = P_max · (speed)³[10]

Yield negative-binomial: ntụpọ na-ejikọta, ya mere yield na-agbada nwayọọ karịa ihe ụdị Poisson na-ebu amụma.

Y = (1 + A·D/α)^(−α), α = 2 (α→∞: Y = e^(−A·D))[3][4][15][14]

Mmụta yield: ọnụọgụ ntụpọ na-ebelata gaa n'ọkwa tozuru etozu ka a na-etinye oge injinia.

D(t+Δt) = D∞ + (D − D∞)·e^(−Δt/τ), τ = 120 h · (0.10 / engineering share)[15][18]Echiche: τ bụ oge e kpọkọtara ihe dị ka okpukpu 100 megide ọnụego mmụta ụlọ ọrụ e kọrọ (4–6.5 % kwa ọnwa, Leachman) ka ọnọdụ ụbọchị 14 gosi mmetụta ahụ.

Obere ihe ndị na-ada na wafer na-agbakwunye ntụpọ egbu egbu n'oke ntinye ikuku.

D_total = D_learn + k · C, k = 4·10⁻⁶ cm⁻² per particle/m³Echiche: ihe na-agbanwe agbanwe ngosi — fab n'ezie na-edozi ọnụego ntụpọ egbu egbu site na data nyocha nke ha.

Yield parametric: oke usoro nkịtị nke dara n'ime oke nkọwapụta; Cpk na-atụ ọkpụkpọ.

Y_param = Φ((USL−μ)/σ) − Φ((LSL−μ)/σ), Cpk = min(USL−μ, μ−LSL)/(3σ)[7][8][19]

SPC: nkezi nke nlele n, na oke njikwa ±3σ/√n na iwu mpaghara.

x̄ ~ N(μ, σ/√n), control limits ±3σ/√n; zone rules (2 of 3 beyond 2σ, 4 of 5 beyond 1σ, 8 on one side)[8][7][12]

Ihe ndị ọzọ na-agbanwe agbanwe ejiri na ụdị a.

8 scanners × 6 wafer-starts/h · metrology −0.5 % capacity per sampled wafer/h · rollback: 2 h at half capacity + 4 wafer-equivalents reworked · drift 0.25 nm/h · crash repair 18 technician-hours · leak crew +2 people for 3 h · tools 150 kW busy / 60 kW idle, fans 150 kW at 100 %Echiche: oke (MTBF, ọnụego mmepụta, k, τ) bụ nhazi ngosi, ọ bụghị data sitere na fab n'ezie.

Ọnụọgụ die zuru oke n'ime wafer 300 mm maka die nwere mpaghara A.

DPW = π·d²/(4A) − π·d/√(2A), d = 300 mm[9]

Enweghị usoro: ihe mmepụta mulberry32 nwere mkpụrụ; nkesa ejiri — uniform, exponential (inverse CDF), normal (Box–Muller), Poisson (Knuth). A na-egosi mkpụrụ ma nwee ike ikekọrịta ya.

Isi mmalite

1. SEMI E10 — Specification for Definition and Measurement of Equipment Reliability, Availability, and Maintainability (RAM) and Utilization — SEMI
2. ISO 14644-1:2015 Cleanrooms and associated controlled environments — Part 1: Classification of air cleanliness by particle concentration — ISO, 2015
3. C. H. Stapper, F. M. Armstrong, K. Saji — Integrated circuit yield statistics — Proceedings of the IEEE 71(4), 1983
4. J. A. Cunningham — The use and evaluation of yield models in integrated circuit manufacturing — IEEE Trans. Semiconductor Manufacturing 3(2), 1990
5. W. J. Hopp, M. L. Spearman — Factory Physics (3rd ed.), ch. 7–8: Little’s law, Kingman (VUT) equation — Waveland Press, 2008
6. J. D. C. Little — A Proof for the Queuing Formula L = λW — Operations Research 9(3), 1961
7. D. C. Montgomery — Introduction to Statistical Quality Control (x̄ charts, process capability Cpk) — Wiley, 2019
8. NIST/SEMATECH e-Handbook of Statistical Methods — 6.3 Univariate and Multivariate Control Charts; 6.1.6 Process capability — NIST
9. Dies-per-wafer estimate DPW = πd²/(4S) − πd/√(2S) (de Vries, “Investigation of gross die per wafer formulas”, IEEE TSM 18(1)) — IEEE, 2005
10. Fan affinity laws: flow ∝ speed, pressure ∝ speed², power ∝ speed³ — U.S. DOE — Improving Fan System Performance: A Sourcebook for Industry
11. EN 1822-1:2019 High efficiency air filters (EPA, HEPA and ULPA) — classification (U15 ≥ 99.9995 % at MPPS) — CEN, 2019
12. Western Electric Statistical Quality Control Handbook (1956) — zone rules for control charts — Western Electric / NIST e-Handbook 6.3.2
13. W. Whyte — Cleanroom Technology: Fundamentals of Design, Testing and Operation (2nd ed.), ch. on dispersion of particles from people; well-mixed room dilution equation — Wiley, 2010
14. Yu. I. Bogdanov, N. A. Bogdanova, V. L. Dshkhunyan — Statistical Yield Modeling for IC Manufacture: Hierarchical Fault Distributions (§2 Compound Poisson distribution, after Eq. (17), p. 4 of the arXiv PDF — large-area clustering negative binomial model: the cluster parameter’s “typical values approximately range from 0.3 to 7”) — arXiv physics/0303039, 2003
15. R. C. Leachman — Yield Modeling and Analysis (Poisson, Murphy, Seeds, negative-binomial models; §8: SMLY survey with C. N. Berglund for International SEMATECH, 2002–03 — yield loss fitted as YL(t) = YL(0)·e^(−λt), Table 2 averages 4.4 / 4.0 / 6.5 %/month at 350 / 250 / 180 nm) — UC Berkeley, IEOR 130 course notes (unpublished), 2014
16. A. Klemmt, L. Mönch — Scheduling jobs with time constraints between consecutive process steps in semiconductor manufacturing (time windows set by process engineering against native oxidation and contamination; jobs that violate them are scrapped) — Proceedings of the 2012 Winter Simulation Conference, 2012
17. NIST/SEMATECH e-Handbook of Statistical Methods — 8.1.6.1 Exponential distribution (constant failure rate) — NIST
18. C. Weber — Yield learning and the sources of profitability in semiconductor manufacturing and process development — IEEE Trans. Semiconductor Manufacturing 17(4), 2004
19. M. Abramowitz, I. Stegun — Handbook of Mathematical Functions, 26.2.17 — NBS, 1964