WIA SOOM Simulators

Semiconductor fab Live model

You run the lithography bay of a 300 mm wafer fab — eight scanners, a cleanroom and a recipe that must stay inside spec. Wafers queue up, tools break, particles drift in and the yield moves with every decision.

What you will learn

Simulator

Time 0 h
Tool availability 100% · Work in process 20 · Cleanroom ISO class 3.4S1⚙S2▶S3▶S4▶S5▶S6▶S7‖S8‖WIP 20▶ 34 wph
  • Productive
  • Standby
  • Engineering
  • Down (repair)
  • Airborne particles

Controls

Wafers released into the bay per hour.

Share of scanner time given to experimental wafer batches that teach the process: less output now, fewer defects later.

Each technician repairs one tool at a time.

More air changes dilute particles; fan power grows with speed cubed.

Every gowned person still sheds particles.

Wafers measured per hour: sharper SPC chart, slightly less capacity.

Takes 3 h and adds 2 people in the room while they work.

2 h at half capacity, then the process is back on target.

Indicators

Good die out
19547/h
Yield
89.8%
normal
Cleanroom ISO class
3.4
normal
Bay cycle time
1.6h
normal
Tool availability100 %
Tool utilization71 %
Engineering time10 %
Wafer starts released34 wph
Work in process20 wafers
Defect density0.110 /cm²
Process capability Cpk1.25 · warning
Out-of-spec (wafer-equivalents)0.0 wph
Bay power1339 kW

Trend

Good die out: — /h250000

SPC sample (CD offset)

SPC sample (CD offset): 0 ⚑+3σ−3σ

Crisis scenarios

Level 1 · Particle excursion

A routine shift on the mobile-chip line. Somewhere above the bay a ceiling filter is about to fail. Keep the cleanroom in class, protect the yield — and do not leave the fans at full speed longer than you need.

  • ISO class back to ≤ 3.6 at the end
  • Never above class 4.55 after the first hour
  • Average yield ≥ 87 % in the first hours of the excursion
  • Average bay power ≤ 1,380 kW in the second half

Level 2 · Scanner crash

The bay runs hot at 38 wafer starts per hour. Three scanners are about to go down at once. Keep the queue from exploding while you get them back, and still ship good die.

  • WIP ≤ 60 wafers at the end
  • Cycle time never above 3.5 h after the crash (queue-time window)
  • At least 900,000 good die in 48 h
  • Release at least 1,600 wafer starts in 48 h (start plan: 34 per hour)

Level 3 · Recipe drift

A new recipe revision went live last night. Nobody knows yet that it slowly shifts the critical dimension. Watch the SPC chart: catch the drift and roll back before wafers fall out of spec.

  • At most 12 out-of-spec wafer-equivalents in total
  • Cpk ≥ 1.2 at the end
  • At least 620,000 good die

Level 2 · New product ramp

A large accelerator chip enters production with an immature process: defect density is high and a 600 mm² die is unforgiving. The line is loaded at 42 wafer starts per hour. You have 14 days. Balance output today against learning for tomorrow.

  • Defect density ≤ 0.08 /cm² at day 14
  • At least 660,000 good die over 14 days

Basis — the model behind the numbers

Every relation the simulator uses, with its source. Constants marked as assumptions are illustrative calibrations.

Equipment states follow SEMI E10: productive, standby, engineering, scheduled and unscheduled down.
Availability = up tools / 8 · Utilization = productive tool-hours / total[1]
Tools fail at random with an exponential time-to-failure; repairs wait for a free technician.
P(fail in Δt) = 1 − e^(−Δt/MTBF), MTBF = 250 h; repair ~ Exp(mean 6 h) once a technician is free[17][1]Assumption: magnitudes (MTBF, generation rates, k, τ) are illustrative calibrations, not data from a real fab.
Little’s law links work in process, throughput and cycle time.
CT = WIP / TH = T0 + queue / TH, T0 = 1 h[6][5]
In a stable line throughput equals the release rate, so a wafer start that is not released is a wafer that never comes out. Wafers waiting too long between steps break the queue-time window.
TH = release rate while u < 1 ⇒ wafers out ≈ Σ starts; queue wait = CT − T0 = queue / TH ≤ queue-time window (3.5 h CT in semi-tool-crash)[5][16]Assumption: the 3.5 h cycle-time limit stands in for a queue-time window; real windows are set step by step by process engineering, and wafers that break them are typically scrapped.
Kingman’s approximation: queue time grows like u/(1−u) — it explodes as utilization nears 100 %.
CTq ≈ ((ca² + ce²)/2) · (u/(1−u)) · te[5]Shown for intuition: the simulator’s queue emerges from random arrivals and random capacity rather than from this formula.
ISO 14644-1 class limit for particles of size D; at 0.1 µm the class is the log of the concentration.
Cn = 10^N · (0.1/D)^2.08 ⇒ N = log10(C≥0.1µm)[2]
Well-mixed room: concentration = generation ÷ (air changes × volume × filter efficiency).
C = G / (ACH · V · η)[13][11]Assumption: magnitudes (MTBF, generation rates, k, τ) are illustrative calibrations, not data from a real fab.
Fan affinity law: power rises with the cube of fan speed.
P_fan = P_max · (speed)³[10]
Negative-binomial yield: defects cluster, so yield falls more slowly than the Poisson model predicts.
Y = (1 + A·D/α)^(−α), α = 2 (α→∞: Y = e^(−A·D))[3][4][15][14]
Yield learning: defect density decays toward a mature level as engineering time is spent.
D(t+Δt) = D∞ + (D − D∞)·e^(−Δt/τ), τ = 120 h · (0.10 / engineering share)[15][18]Assumption: τ is time-compressed about 100× versus reported industry learning rates (4–6.5 % per month, Leachman) so that a 14-day scenario shows the effect.
Particles that land on wafers add killer defects in proportion to air concentration.
D_total = D_learn + k · C, k = 4·10⁻⁶ cm⁻² per particle/m³Assumption: an illustrative constant — real fabs calibrate killer-defect rates from their own inspection data.
Parametric yield: the share of a normal process that falls inside the spec limits; Cpk measures the margin.
Y_param = Φ((USL−μ)/σ) − Φ((LSL−μ)/σ), Cpk = min(USL−μ, μ−LSL)/(3σ)[7][8][19]
SPC: averages of n samples, with ±3σ/√n control limits and zone rules.
x̄ ~ N(μ, σ/√n), control limits ±3σ/√n; zone rules (2 of 3 beyond 2σ, 4 of 5 beyond 1σ, 8 on one side)[8][7][12]
Other operating constants used by the model.
8 scanners × 6 wafer-starts/h · metrology −0.5 % capacity per sampled wafer/h · rollback: 2 h at half capacity + 4 wafer-equivalents reworked · drift 0.25 nm/h · crash repair 18 technician-hours · leak crew +2 people for 3 h · tools 150 kW busy / 60 kW idle, fans 150 kW at 100 %Assumption: magnitudes (MTBF, generation rates, k, τ) are illustrative calibrations, not data from a real fab.
Gross dies per 300 mm wafer for a die of area A.
DPW = π·d²/(4A) − π·d/√(2A), d = 300 mm[9]

Randomness: a seeded mulberry32 generator; distributions used — uniform, exponential (inverse CDF), normal (Box–Muller), Poisson (Knuth). The seed is shown and shareable.

Sources

  1. SEMI E10 — Specification for Definition and Measurement of Equipment Reliability, Availability, and Maintainability (RAM) and Utilization — SEMI
  2. ISO 14644-1:2015 Cleanrooms and associated controlled environments — Part 1: Classification of air cleanliness by particle concentration — ISO, 2015
  3. C. H. Stapper, F. M. Armstrong, K. Saji — Integrated circuit yield statistics — Proceedings of the IEEE 71(4), 1983
  4. J. A. Cunningham — The use and evaluation of yield models in integrated circuit manufacturing — IEEE Trans. Semiconductor Manufacturing 3(2), 1990
  5. W. J. Hopp, M. L. Spearman — Factory Physics (3rd ed.), ch. 7–8: Little’s law, Kingman (VUT) equation — Waveland Press, 2008
  6. J. D. C. Little — A Proof for the Queuing Formula L = λW — Operations Research 9(3), 1961
  7. D. C. Montgomery — Introduction to Statistical Quality Control (x̄ charts, process capability Cpk) — Wiley, 2019
  8. NIST/SEMATECH e-Handbook of Statistical Methods — 6.3 Univariate and Multivariate Control Charts; 6.1.6 Process capability — NIST
  9. Dies-per-wafer estimate DPW = πd²/(4S) − πd/√(2S) (de Vries, “Investigation of gross die per wafer formulas”, IEEE TSM 18(1)) — IEEE, 2005
  10. Fan affinity laws: flow ∝ speed, pressure ∝ speed², power ∝ speed³ — U.S. DOE — Improving Fan System Performance: A Sourcebook for Industry
  11. EN 1822-1:2019 High efficiency air filters (EPA, HEPA and ULPA) — classification (U15 ≥ 99.9995 % at MPPS) — CEN, 2019
  12. Western Electric Statistical Quality Control Handbook (1956) — zone rules for control charts — Western Electric / NIST e-Handbook 6.3.2
  13. W. Whyte — Cleanroom Technology: Fundamentals of Design, Testing and Operation (2nd ed.), ch. on dispersion of particles from people; well-mixed room dilution equation — Wiley, 2010
  14. Yu. I. Bogdanov, N. A. Bogdanova, V. L. Dshkhunyan — Statistical Yield Modeling for IC Manufacture: Hierarchical Fault Distributions (§2 Compound Poisson distribution, after Eq. (17), p. 4 of the arXiv PDF — large-area clustering negative binomial model: the cluster parameter’s “typical values approximately range from 0.3 to 7”) — arXiv physics/0303039, 2003
  15. R. C. Leachman — Yield Modeling and Analysis (Poisson, Murphy, Seeds, negative-binomial models; §8: SMLY survey with C. N. Berglund for International SEMATECH, 2002–03 — yield loss fitted as YL(t) = YL(0)·e^(−λt), Table 2 averages 4.4 / 4.0 / 6.5 %/month at 350 / 250 / 180 nm) — UC Berkeley, IEOR 130 course notes (unpublished), 2014
  16. A. Klemmt, L. Mönch — Scheduling jobs with time constraints between consecutive process steps in semiconductor manufacturing (time windows set by process engineering against native oxidation and contamination; jobs that violate them are scrapped) — Proceedings of the 2012 Winter Simulation Conference, 2012
  17. NIST/SEMATECH e-Handbook of Statistical Methods — 8.1.6.1 Exponential distribution (constant failure rate) — NIST
  18. C. Weber — Yield learning and the sources of profitability in semiconductor manufacturing and process development — IEEE Trans. Semiconductor Manufacturing 17(4), 2004
  19. M. Abramowitz, I. Stegun — Handbook of Mathematical Functions, 26.2.17 — NBS, 1964

Who does this for a living

Educational model — not for operational decisions. Real sites calibrate every constant to their own equipment and data.