💠 Warshadda semiconductor-ka Qaabka tooska ah

Aasaas — moodelka ka dambeeya tirooyinka

Xiriir kasta oo jilaha isticmaalo, iyo ilaha uu ka yimid. Mudnaanta lagu calaamadiyay malo-awaal waa hagaajin muunad ah.

Xaaladaha qalabka waxay raacaan SEMI E10: wax-soo-saar, sugitaan, injineernimo, joogsi la qorsheeyay iyo mid aan la qorsheynin.

Availability = up tools / 8 · Utilization = productive tool-hours / total[1]

Qalabku si aan kala sooc lahayn ayuu u guuldareystaa isagoo leh waqti-ilaa-guuldarro tibaax ah; dayactirradu waxay sugaan farsamoyaqaan bannaan.

P(fail in Δt) = 1 − e^(−Δt/MTBF), MTBF = 250 h; repair ~ Exp(mean 6 h) once a technician is free[17][1]Malo-awaal: cabbirrada (MTBF, heerarka soo-saarka, k, τ) waa hagaajin muunad ah, ma aha xog warshad dhab ah.

Sharciga Little wuxuu isku xidhaa shaqada socota, wax-soo-saarka iyo waqtiga wareegga.

CT = WIP / TH = T0 + queue / TH, T0 = 1 h[6][5]

Khad deggan, wax-soo-saarku wuxuu la mid yahay heerka sii-deynta, sidaas darteed bilaw wafer oo aan la sii dayn waa wafer aan marnaba soo bixin. Wafer-ada sugaya muddo aad u dheer tallaabooyinka u dhexeeya waxay jebiyaan daaqadda waqti-safka.

TH = release rate while u < 1 ⇒ wafers out ≈ Σ starts; queue wait = CT − T0 = queue / TH ≤ queue-time window (3.5 h CT in semi-tool-crash)[5][16]Malo-awaal: xadka waqtiga wareegga ee 3.5 h wuxuu matalaa daaqad waqti-saf; daaqadaha dhabta ah waxaa tallaabo-tallaabo u dejiya injineernimada habka, wafer-ada jebiyana inta badan waa la tuuraa.

Qiyaasta Kingman: waqtiga safku wuxuu kortaa sida u/(1−u) — wuu qarxaa marka isticmaalku u dhowaado 100 %.

CTq ≈ ((ca² + ce²)/2) · (u/(1−u)) · te[5]Waxaa loo muujiyay si fahan loo helo: safka jilaha wuxuu ka dhashaa imaatin aan kala sooc lahayn iyo awood aan kala sooc lahayn halkii uu ka imaan lahaa qaacidadan.

Xadka fasalka ISO 14644-1 ee walxaha cabbirka D; 0.1 µm fasalku waa logarithm-ka urursanaanta.

Cn = 10^N · (0.1/D)^2.08 ⇒ N = log10(C≥0.1µm)[2]

Qol si fiican isku-dhafan: urursanaan = soo-saar ÷ (beddelka hawada × mugga × waxtarka shaandhada).

C = G / (ACH · V · η)[13][11]Malo-awaal: cabbirrada (MTBF, heerarka soo-saarka, k, τ) waa hagaajin muunad ah, ma aha xog warshad dhab ah.

Sharciga isku-xidhnaanta marawaxadda: awoodu waxay kortaa kuubka xawaaraha marawaxadda.

P_fan = P_max · (speed)³[10]

Wax-soo-saarka binomial-ka taban: cilladuhu way kulmaan, sidaas darteed wax-soo-saarku wuu gaabis u dhacaa marka loo eego sida moodelka Poisson saadaaliyo.

Y = (1 + A·D/α)^(−α), α = 2 (α→∞: Y = e^(−A·D))[3][4][15][14]

Barashada wax-soo-saarka: cufnaanta cilladuhu waxay hoos ugu dhacdaa heer qaan-gaar ah marka waqtiga injineernimada la isticmaalo.

D(t+Δt) = D∞ + (D − D∞)·e^(−Δt/τ), τ = 120 h · (0.10 / engineering share)[15][18]Malo-awaal: τ waa la cufay waqti ku dhawaad 100 jibaar marka loo eego heerarka barashada warshadaha ee la soo wariyay (4–6.5 % bishii, Leachman) si xaalad 14 maalmood ahi saamaynta u muujiso.

Walxaha yar-yar ee wafer-ada dul dhaca waxay ku daraan cillado dilaa ah iyadoo la raacayo urursanaanta hawada.

D_total = D_learn + k · C, k = 4·10⁻⁶ cm⁻² per particle/m³Malo-awaal: mudnaan muunad ah — warshadaha dhabta ahi waxay hagaajiyaan heerarka cilladaha dilaaga ah xogtooda hubinta.

Wax-soo-saarka halbeegga: qaybta habka caadiga ah ee gudaha ugu dhacda xadka qeexitaanka; Cpk wuxuu cabbiraa daahidda.

Y_param = Φ((USL−μ)/σ) − Φ((LSL−μ)/σ), Cpk = min(USL−μ, μ−LSL)/(3σ)[7][8][19]

SPC: celceliska n muunad, oo leh xadka xakamaynta ±3σ/√n iyo xeerarka aagagga.

x̄ ~ N(μ, σ/√n), control limits ±3σ/√n; zone rules (2 of 3 beyond 2σ, 4 of 5 beyond 1σ, 8 on one side)[8][7][12]

Mudnaanta kale ee hawlgalka ee uu moodelku isticmaalo.

8 scanners × 6 wafer-starts/h · metrology −0.5 % capacity per sampled wafer/h · rollback: 2 h at half capacity + 4 wafer-equivalents reworked · drift 0.25 nm/h · crash repair 18 technician-hours · leak crew +2 people for 3 h · tools 150 kW busy / 60 kW idle, fans 150 kW at 100 %Malo-awaal: cabbirrada (MTBF, heerarka soo-saarka, k, τ) waa hagaajin muunad ah, ma aha xog warshad dhab ah.

Tirada guud ee chip-yada wafer 300 mm ah ee chip leh aag A.

DPW = π·d²/(4A) − π·d/√(2A), d = 300 mm[9]

Aan-kala-sooc: abuurahaha mulberry32 oo abuur leh; qaybinta la isticmaalay — isku-mid, tibaax (CDF rogan), caadi (Box–Muller), Poisson (Knuth). Abuurka waa la muujiyaa waana la wadaagi karaa.

Ilaha

1. SEMI E10 — Specification for Definition and Measurement of Equipment Reliability, Availability, and Maintainability (RAM) and Utilization — SEMI
2. ISO 14644-1:2015 Cleanrooms and associated controlled environments — Part 1: Classification of air cleanliness by particle concentration — ISO, 2015
3. C. H. Stapper, F. M. Armstrong, K. Saji — Integrated circuit yield statistics — Proceedings of the IEEE 71(4), 1983
4. J. A. Cunningham — The use and evaluation of yield models in integrated circuit manufacturing — IEEE Trans. Semiconductor Manufacturing 3(2), 1990
5. W. J. Hopp, M. L. Spearman — Factory Physics (3rd ed.), ch. 7–8: Little’s law, Kingman (VUT) equation — Waveland Press, 2008
6. J. D. C. Little — A Proof for the Queuing Formula L = λW — Operations Research 9(3), 1961
7. D. C. Montgomery — Introduction to Statistical Quality Control (x̄ charts, process capability Cpk) — Wiley, 2019
8. NIST/SEMATECH e-Handbook of Statistical Methods — 6.3 Univariate and Multivariate Control Charts; 6.1.6 Process capability — NIST
9. Dies-per-wafer estimate DPW = πd²/(4S) − πd/√(2S) (de Vries, “Investigation of gross die per wafer formulas”, IEEE TSM 18(1)) — IEEE, 2005
10. Fan affinity laws: flow ∝ speed, pressure ∝ speed², power ∝ speed³ — U.S. DOE — Improving Fan System Performance: A Sourcebook for Industry
11. EN 1822-1:2019 High efficiency air filters (EPA, HEPA and ULPA) — classification (U15 ≥ 99.9995 % at MPPS) — CEN, 2019
12. Western Electric Statistical Quality Control Handbook (1956) — zone rules for control charts — Western Electric / NIST e-Handbook 6.3.2
13. W. Whyte — Cleanroom Technology: Fundamentals of Design, Testing and Operation (2nd ed.), ch. on dispersion of particles from people; well-mixed room dilution equation — Wiley, 2010
14. Yu. I. Bogdanov, N. A. Bogdanova, V. L. Dshkhunyan — Statistical Yield Modeling for IC Manufacture: Hierarchical Fault Distributions (§2 Compound Poisson distribution, after Eq. (17), p. 4 of the arXiv PDF — large-area clustering negative binomial model: the cluster parameter’s “typical values approximately range from 0.3 to 7”) — arXiv physics/0303039, 2003
15. R. C. Leachman — Yield Modeling and Analysis (Poisson, Murphy, Seeds, negative-binomial models; §8: SMLY survey with C. N. Berglund for International SEMATECH, 2002–03 — yield loss fitted as YL(t) = YL(0)·e^(−λt), Table 2 averages 4.4 / 4.0 / 6.5 %/month at 350 / 250 / 180 nm) — UC Berkeley, IEOR 130 course notes (unpublished), 2014
16. A. Klemmt, L. Mönch — Scheduling jobs with time constraints between consecutive process steps in semiconductor manufacturing (time windows set by process engineering against native oxidation and contamination; jobs that violate them are scrapped) — Proceedings of the 2012 Winter Simulation Conference, 2012
17. NIST/SEMATECH e-Handbook of Statistical Methods — 8.1.6.1 Exponential distribution (constant failure rate) — NIST
18. C. Weber — Yield learning and the sources of profitability in semiconductor manufacturing and process development — IEEE Trans. Semiconductor Manufacturing 17(4), 2004
19. M. Abramowitz, I. Stegun — Handbook of Mathematical Functions, 26.2.17 — NBS, 1964